The present invention is generally in the field of bipolar transistor circuits. In particular, it is in the field of biasing methods and circuits for bipolar transistor amplifiers.
The need to bias transistors for proper circuit operation is known, as are methods and circuits for providing the necessary bias voltages and currents. Known methods and circuits include emitter, base, and collector biasing. Each method and circuit has certain advantages, but no known method is without significant disadvantages. A single emitter bias circuit is shown in FIG. 1. A fixed voltage V.sub.Ref is applied to the base of transistor 13, turning it on. In turn, a current I.sub.c1 flows through transistor 11. Although the circuit is easy to make and allows for the accurate determination of I.sub.c1, it is very inefficient. The collector voltage swing available for transistor 11 is limited largely by V.sub.Ref. This collector voltage swing over the amplifier is herein referenced as the voltage headroom of the amplifier.
Collector biasing, shown in FIG. 2, has the important advantage of coupling transistor 25's emitter to ground, which provides more voltage headroom for the amplifier. The disadvantages result from having resistor 21 coupled between V.sub.cc, the emitter of transistor 23, and the collector of transistor 25. This creates a load impedance on transistor 25 which is not always desirable and restricts the available voltage headroom. Load impedance and bias conditions which are coupled limit the subsequent options for tuning the amplifier and varying its efficiency. The biasing network is closely coupled to the circuit's input and output and the output signal can flow back through the bias network and cause the circuit to oscillate. Additional capacitance may be needed in the feedback pathway to prevent such oscillation. Despite this, collector biasing is useful in low noise amplifiers, as there is no resistive impedance on the emitter to add noise.
A first base biasing circuit is shown in FIG. 3. The current through resistor 31, I.sub.set, is roughly equal to V.sub.cc -C.sub.be (the base-emitter voltage drop of a transistor) divided by the combination of resistors 31 and 37. Proper sizing of resistor 39 and transistor 35 results in the current through transistor 35's collector, I.sub.c2, having a value of 10I.sub.set. The voltage headroom can be as large as in the collector biasing circuit shown in FIG. 2 or larger, as the voltage at transistor 35's emitter is low (.about.200 millivolts). The circuit functions equally well in linear and non-linear amplifiers and has adequate first order temperature compensation as the V.sub.be of all the NPN transistors varies roughly equally with variations in temperature. As the circuit's input impedance is difficult to tune, it tends to perform poorly in monolithic integrated circuit ("IC") applications. The circuit is not compensated for variations in .beta., which can vary by a factor of 2 to 3 times from wafer to wafer. Temperature induced .beta. variations also affect the circuit's bias point and performance. Additionally, short of disconnecting or otherwise turning off V.sub.cc, there is no simple way of powering down the circuit.
A second base biasing circuit is shown in FIG. 4. I.sub.Set2 equals V.sub.Ref -V.sub.be divided by resistor 47. Through the principle of current mirroring and the use of proper component values, I.sub.c3 equals five times I.sub.Set and I.sub.c4 is equal to four times I.sub.c3. In this circuit, V.sub.Ref is supplied by a band gap reference voltage source which is independent of supply voltage V.sub.cc and is temperature compensated. The circuit as a whole is fully temperature compensated and the NPN transistors are more independent of .beta. variations. The input impedance of this circuit is greater than that of the circuit shown in FIG. 3. Turning off the circuit shown in FIG. 4 is easily done by turning off the band gap reference voltage source. The circuit has the major disadvantage that the input signal and the bias signal are coupled together. I.sub.c3 modulates with the input and resistor 42 feeds back to transistor 50 through PNP transistor 44. The feedback signal distorts the input signal and can lead to oscillation. The bias circuit also requires a relatively high V.sub.cc, as the voltage drops over resistors 42 and 45 are large in order to isolate the bias current and signal currents.
There remains a need for a bias circuit which can provide the maximum possible voltage headroom while simultaneously separating the input signal and the bias signal while operating at a low supply voltage. Full temperature compensation and high input impedance are also desirable.